Office: Packard Lab Room 404A 

19 Memorial Dr W

Bethlehem, PA 18015

Phone: 610-758-4421



Dr. Guo is an associate professor in the Department of Electrical and Computer Engineering at Lehigh University. Dr. Guo received her Ph.D. degree in Electrical and Computer Engineering from the University of Rochester in 2015, and received the IBM Ph.D. Fellowship twice. Dr. Guo’s research interests are in the broad area of computer architecture, with an emphasis on leveraging emerging technologies to build energy-efficient microprocessors and memory systems. Dr. Guo is an IEEE senior member and a recipient of the National Science Foundation CAREER Award, the P. C. Rossin Assistant Professorship, and the Lawrence Berkeley National Laboratory Computing Sciences Research Pathways Fellowship. 

Dr. Guo is on leave starting May, 2022.


Selected Publications (Full List)

Hesam Shabani, Abhishek Singh, Bishoy Youhana, and Xiaochen Guo, “HIRAC: A Hierarchical Accelerator with Sorting-based Packing for SpGEMMs in DNN Applications”, in proceedings of the 29th IEEE International Symposium on High-Performance Computer Architecture (HPCA), Montreal, QC, Canada, Feb. 2023.

Chao Zhang, Maximilian Bremer, Cy Chan, John Shalf, and Xiaochen Guo, “ASA: Accelerating Sparse Accumulation in Column-wise SpGEMM,” in ACM Transactions on Architecture and Code Optimization (TACO). vol. 19, no. 4, Article 49, Dec. 2022.

Abhishek Singh, Shail Dave, PanteA Zardoshti, Robert Brotzman, Chao Zhang, Xiaochen Guo, Aviral Shrivastava, Gang Tan, and Michael Spear, “SPX64: A Scratchpad Memory for General-Purpose Microprocessors,” in ACM Transactions on Architecture and Code Optimization (TACO). vol. 18, no. 1, Article 14, Jan. 2021.

Chao Zhang, Yuan Zeng, John Shalf, and Xiaochen Guo, “RnR: A Software-Assisted Record-and-Replay Hardware Prefetcher,” in Proceedings of the 53rd IEEE/ACM International Symposium on Microarchitecture (MICRO), Virtual Conference, October 2020.

Chao Zhang, Yuan Zeng, and Xiaochen Guo, “Scrabble: A Fine-Grained Cache with Adaptive Merged Block,” in IEEE Transactions on Computers (TC), vol. 69, no. 1, pp. 112-125, 1 Jan. 2020.

Xiaochen Guo, Mahdi Nazm Bojnordi, Qing Guo, and Engin Ipek, “Sanitizer: Mitigating the Impact of Expensive ECC Checks on STT-MRAM based Main Memories,” in IEEE Transactions on Computers (TC), vol. 67, no. 6, pp. 847-860, 1 June 2018.

Chao Zhang and Xiaochen Guo, “Enabling Efficient Fine-Grained DRAM Activations with Interleaved I/O,” in Proceedings of the International Symposium on Low Power Electronics and Design (ISLPED), Taipei, Taiwan, July 2017.

Ravi Patel, Xiaochen Guo, Qing Guo, Engin Ipek, and Eby G. Friedman, “Reducing Switching Latency and Energy in STT-MRAM Caches With Field-Assisted Writing,” in IEEE Transactions on Very Large Scale Integration Systems (TVLSI), vol. 24, no. 1, pp. 129-138, Jan. 2016.

Qing Guo, Xiaochen Guo, Ravi Patel, Engin Ipek, and Eby G. Friedman, “AC-DIMM: Associative Computing with STT-MRAM,” in Proceedings of the 40th International Symposium on Computer Architecture (ISCA), Tel-Aviv, Israel, June 2013.

Qing Guo, Xiaochen Guo, Yuxin Bai, and Engin Ipek, “A Resistive TCAM Accelerator for Data Intensive Computing,” in Proceedings of the 44th International Symposium on Microarchitecture (MICRO), Porto Alegre, Brazil, December 2011.

Xiaochen Guo, Engin Ipek, and Tolga Soyata, “Resistive Computation: Avoiding the Power Wall with Low-Leakage, STT-MRAM Based Computing,” in Proceedings of the 37th International Symposium on Computer Architecture (ISCA), Saint-Malo, France, June 2010.