** About Me **

I am interested in spiking neural network algorithm design and its implementations; energy efficient architecture designs; and cache-memory data movement optimization. My research currently focuses on designing learning algorithms for biological neural networks. I have background in hardware architecture, machine learning, and computational neuroscience. My advisor is Prof. Xiaochen Guo. Here is my Recent CV: Yuan_Zeng_2022.

Publications

[ICONS’21] Yuan Zeng, Terrence C. Stewart, Zubayer Ibne Ferdous, Yevgeny Berdichevsky, and Xiaochen Guo, “Temporal Learning with Biologically Fitted SNN Models,” in proceedings of the International Conference on Neuromorphic Systems (ICONS), Virtual Conference, July 2021

[Frontier’21] Yuan Zeng, Zubayer Ibne Ferdous, Weixiang Zhang, Mufan Xu, Anlan Yu, Drew Patel, Valentin Post, Xiaochen Guo, Yevgeny Berdichevsky, and Zhiyuan Yan, “Understanding the Impact of Neural Variations and Random Connections on Inference“, in Frontiers in Computational Neuroscience 15 (2021): 44.

[MICRO’20] Chao Zhang, Yuan Zeng, John Shalf, and Xiaochen Guo, “RnR: A Software- Assisted Record-and-Replay Hardware Prefetcher,” in Proceedings of the 53rd IEEE/ACM International Symposium on Microarchitecture (MICRO), Virtual Conference, October 2020.

[TC’19] Chao Zhang, Yuan Zeng, and Xiaochen Guo “Scrabble: A Fine-Grained Cache with Adaptive Merged Block“, IEEE Transactions on Computers (TC), 2019.    

[ICASSP’18] Yuan Zeng, Kevin Devincentis, Yao Xiao, Zubayer Ibne Ferdous, Xiaochen Guo, Zhiyuan Yan, and Yevgeny Berdichevsky, “A Supervised STDP-based Training Algorithm for Living Neural Networks“, International Conference on Acoustics, Speech and Signal Processing (ICASSP), Calgary, Canada, April 2018.    

[MEMSYS’17] Yuan Zeng, Xiaochen Guo, “Long Short Term Memory Based Hardware Prefetcher“, in Proceeding of the international Symposium on Memory System (MEMSYS), Washington DC, October 2017.